The present invention relates generally to techniques for connecting the optical and electrical device components. More particularly, the invention relates to LTCC (low temperature co-fired ceramic) structures for use in optical subassemblies.
Many computer and communication networks being built today, including the Internet, are using fiber optic cabling instead of copper wire. With fiber optic cabling, data is transmitted using light signals, not electrical signals. For example, a logical one may be represented by a light pulse of a specific duration and frequency, a logical zero may be represented by the absence of a light pulse for the same duration. Optical fiber has the advantage of having a much greater bandwidth than copper wire.
While fiber optic cabling is very efficient for transferring data, the use of light signals to process data is still very difficult. For instance, currently there is no efficient way to xe2x80x9cstorexe2x80x9d light signals representative of data. Networks therefore use fiber optics for transmitting data between nodes and silicon chips to process the data within computer nodes. This is accomplished by using fiber optic transceivers, which convert light signals from a fiber optic cable into electrical signals, and vice versa. FIG. 1 illustrates a perspective view of an exemplary optoelectronic module 100 that can be used to form an optical transceiver.
Optoelectronic module 100 includes a semiconductor chip subassembly (CSA) 102 and an optical subassembly (OSA) 104. CSA 102 is a packaged semiconductor device. As shown in FIG. 1, CSA 102 is a rectangular block of molding material 106 that has electrical contacts 108 exposed through its bottom and side surfaces. Within the block of molding material 106 is a semiconductor die that is electrically connected to contacts 108. For instance, wire bonds can be used for such connections. Another aspect of CSA 102 that cannot be seen is the up-linking contacts on the top surface of CSA 102. These up-linking contacts are also electrically connected to the encapsulated semiconductor die and therefore provide the electrical communication between the semiconductor die and OSA 104. The specific CSA 102 that is shown is a leadless leadframe semiconductor package (LLP). However, it should be understood that CSA 102 can be formed of various types of molded packages.
A conventional OSA 104 includes a conventional backing block 110, a circuitry substrate 112, and photonic devices 114. Backing block 110 has a front surface 116 that supports circuitry substrate 112 and photonic devices 114, which are attached to circuitry substrate 112. A conventional backing block 110 can be formed of a variety of materials such as a ceramic material, polyethylene ether ketone (PEEK), or liquid crystal polymer (LCP). Examples of such conventional OSA""s 104 and backing blocks 104 are known to persons having ordinary skill in the art. One typical example of such a conventional backing block is described, for example, in the U.S. patent application Ser. No. 10/165/711, entitled xe2x80x9cCERAMIC OPTICAL SUB-ASSEMBLY FOR OPTO-ELECTRONIC MODULES,xe2x80x9d filed on Jun. 6, 2002.
In conventional implementation, a circuitry substrate 112 is attached to a front surface 116 of backing block 110, wraps around the bottom-front corner of backing block 110, and covers most of the bottom surface of backing block 110. Traces of the circuitry substrate 112 run from photonic devices 114 on the front surface to the bottom surface of backing block 110 where they make contact with the up-linking contacts of CSA 102. In an effort to maximize the number of electrical connections possible, size dimensions of the foregoing devices are small. However, even though the size dimensions are made small, the fact that the circuitry substrate 112 is formed only at the surface (or in some implementations two layers deep) of the backing block 110 limits the overall number of electrical connections that can be made from the photonic devices 114 to contacts of the CSA 102.
Additionally, such surface mounted circuitry substrates 112 can suffer from xe2x80x9ccross-talkxe2x80x9d. In typical implementation, size dimensions involved with circuitry substrate 112 are small and cause the circuit traces to be positioned very close to each other. The small size is advantageous in the same way that small sizes for most electronic devices are advantageous. However, the close proximity of the traces can cause xe2x80x9ccross-talk,xe2x80x9d especially at high operational frequencies. Cross-talk is the electrical interference between two or more electrically conducting elements. Such cross-talk can drastically reduce the performance of optoelectronic device 100.
FIG. 2 is a schematic depiction of a conventional backing block 204 (depicted upside down) showing a bottom side 201 and a facing side 202. Commonly, the photonic devices 214 are formed on the facing side 202 of the block 204 and electrically connected to contact pads 215 on the bottom side 201. The photonic devices 214 are electrically connected to contact pads 215 using surface metallization techniques. Typically, the photonic devices 214 are electrically connected to contact pads 215 using electric traces (or leads) 216 formed on a special contact tape that adheres to the block 204. A problem with this implementation is that the electric traces 216 have a tendency to fail in the region where the tape bends over the edge 217 of the block 204.
In view of the foregoing, what is needed is an efficient technique for forming high density electrical connections from the photonic devices of an optical device to an associated semiconductor chip device such that the connections exhibit high circuit density and low levels of cross-talk.
The present invention is directed to a high performance and small-scale circuitry substrate and supporting block used in optical sub-assemblies. In one embodiment an optical sub-assembly (OSA) suitable for optical interconnection with optical fibers and electrical interconnection with a chip sub-assembly (CSA) is formed. The OSA includes a ceramic block having a first surface and a second surface, the ceramic block being formed using one of low temperature co-fired ceramic (LTCC) and high temperature co-fired ceramic (HTCC) techniques. Photonic devices are formed on the first surface of the ceramic block and electrical contacts are formed on a second surface of the block. The electrical contacts being suitable for electrical communication with a chip sub-assembly. Moreover, the electrical connections being formed so that they pass internally through the ceramic block to electrically interconnect the photonic devices on the first face of the block with the electrical contacts on the second face of the block.
Another embodiment includes a ceramic block having a first face and a second face. The block being formed using one of low temperature co-fired ceramic (LTCC) and high temperature co-fired ceramic (HTCC) techniques. The first face of the ceramic block has at least one photonic device formed thereon. Contact pads are formed on the second face of the ceramic block. The block also includes electrical connections that are electrically connected to the photonic devices and pass through internal portions of the ceramic block to so that the electrical connections can electrically the photonic devices to a chip sub-assembly (CSA). The electrical connections can include both signal connections and ground connections. Moreover, embodiments can include internal shielding layers. The configuration of the block can be designed so that cross-talk is reduced, low levels of ground-bounce and electrical parasitics are exhibited, and optimal impedance levels can be obtained. The circuitry substrate can be advantageously used to form an optical sub-assembly (OSA) used in an optoelectronic module.
In another embodiment, the ceramic block includes a plurality of ceramic layers formed using one of low temperature co-fired ceramic (LTCC) techniques and high temperature co-fired ceramic (HTCC) techniques. The ceramic block includes a front surface and a bottom surface. The front surface of the block includes a plurality of contact pads with a plurality of photonic devices. The bottom surface includes a plurality of solder pads. The block further includes internal electric contact planes having at least one electric contact line formed thereon such that the at least one electric contact line passes internally through the ceramic block and is in electrical communication with the contact pads and associated solder pads. The contact pads having wire bonds for electrically connecting the contact pads with the photonic devices. The block also includes at least one internal ground plane having at least one ground contact line formed thereon such that the at least one ground contact line passes internally through the ceramic block and is in electrical communication with selected solder pads. The module further including a semiconductor chip sub assembly (CSA) having a top surface that has exposed up-linking contacts that are in electrical contact with the solder pads formed on the bottom surface of the ceramic block when the ceramic block is placed onto the top surface of the CSA.
These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying figures, which illustrate by way of example the principles of the invention.